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general description maxim? redesigned dg411/dg412/dg413 analogswitches now feature low on-resistance matching between switches (3 max) and guaranteed on-resis- tance flatness over the signal range ( 4 max). these low on-resistance switches conduct equally well ineither direction. they guarantee low charge injection, low power consumption, and an esd tolerance of 2000v minimum per method 3015.7. the new design offers lower off-leakage current over temperature (less than 5na at +85?). the dg411/dg412/dg413 are quad, single-pole/sin- gle-throw (spst) analog switches. the dg411 is nor- mally closed (nc), and the dg412 is normally open (no). the dg413 has two nc switches and two no switches. switching times are less than 150ns max for t on and less than 100ns max for t off . these devices operate from a single +10v to +30v supply, or bipolar?.5v to ?0v supplies. maxim? improved dg411/dg412/dg413 are fabricated with a 44v silicon- gate process. ________________________applications sample-and-hold circuits communication systems test equipment battery-operated systems heads-up displays pbx, pabx guidance & control systems audio signal routing military radios ______________________new features ? ? plug-in upgrade for industry-standarddg411/dg412/dg413 ? ? improved r ds(on) match between channels (3 max) ? ? guaranteed r flat(on) over signal range ( 4 ) ? ? improved charge injection (10pc max) ? ? improved off-leakage current over temperature(< 5na at +85?) ? ? withstand electrostatic discharge (2000v min)per method 3015.7 __________________existing features ? ? low r ds(on) (35 max) ? ? single-supply operation +10v to +30v ? ? bipolar-supply operation ?.5v to ?0v ? ? low power consumption (35 w max) ? ? rail-to-rail signal handling ? ? ttl/cmos-logic compatible ordering information dg411/dg412/dg413 improved, quad, spst analog switches ________________________________________________________________ maxim integrated products 1 switches shown for logic ??input dip/so/tssop dg412 logic switch 01 off on top view dip/so/tssop dg411 logic switch 01 on off dip/so/tssop dg413 logic switches 1, 4 01 off on switches 2, 3 on off 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 in2 d2 s2 v+ v- s1 d1 in1 dg413 v l s3d3 in3 in4 d4 s4 gnd 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 in2d2 s2 v+ v- s1 d1 in1 dg411 v l s3d3 in3 in4 d4 s4 gnd 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 in2 d2 s2 v+ v- s1 d1 in1 dg412 v l s3d3 in3 in4 d4 s4 gnd pin configurations/functional diagrams/truth tables 19-4728; rev 7; 9/08 ordering information continued at end of data sheet. ? contact factory for dice specifications. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations and functional diagrams continued at end of data sheet. part temp range pin-package dg411 cj 0? to +70? 16 plastic dip dg411cue 0? to +70? 16 tssop dg411eue -40? to +85? 16 tssop dg411cy 0? to +70? 16 narrow so dg411c/d 0? to +70? dice? downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics?ual supplies (v+ = 15v, v- = -15v, v l = 5v, v gnd = 0v, v inh = 2.4v, v inl = 0.8v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: signals on s, d, or in exceeding v+ or v- are clamped by internal diodes. limit forward current to maximum current rating. (all voltages referenced to v-.) v+.........................................................................................44v gnd .....................................................................................25v v l .....................................................(gnd -0.3v) to (v+ +0.3v) digital inputs, v s , v d (note 1)........(v- -2v) to (v+ +2v) or 30ma (whichever occurs first) continuous current (any terminal) ......................................30ma peak current (pulsed at 1ms, 10% duty cycle max) ............................100ma continuous power dissipation (t a = +70?) 16-pin plastic dip (derate 10.53mw/? above +70?) .842mw 16-pin narrow so (derate 8.70mw/? above +70?) ...696mw 16-pin cerdip (derate 10.00mw/? above +70?)......800mw 16-pin tssop (derate 6.7mw/? above +70?) ...........457mw 16-pin qfn (derate 19.2mw/? above +70?) ...........1538mw operating temperature ranges dg41_c_ ..............................................................0? to +70? dg41_d_ ...........................................................-40? to +85? dg41_ak_ .......................................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? 17 30 a c, d -40 40 -10 10 -10 10 -0.25 -0.10 0.25 6 5 a a a t a = t min to t max t a = t min to t max c, d c, d c, d t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = +25? t a = +25? v+ = 16.5v,v- = -16.5v, v d = ?5.5v, v s = ?5.5v v+ = 16.5v,v- = -16.5v, v d = ?5.5v, v s = 15.5v (note 3) v+ = 16.5v,v- = -16.5v, v d = ?5.5v, v s = 15.5v v+ = 15v, v- = -15v,v d = ?0v, i s = -10ma v+ = 13.5v,v- = -13.5v, v d = ?.5v, i s = -10ma v+ = 15v, v- = -15v,v d = ?v, 0v, i s = -10ma conditions na -20 20 i d(on) + i s(on) drain on-leakage current(note 7) -0.4 -0.1 0.4 i d(off) na -5 5 drain off-leakage current(note 7) -5 5 na i s(off) source off-leakage current(note 7) -0.25 -0.10 0.25 4 r flat(on) on-resistance flatness(note 4) v -15 15 v analog analog signal range ? r ds(on) on-resistancematch between channels (note 4) 3 17 45 45 r ds(on) drain-sourceon-resistance units min typ max (note 2) symbol parameter c, d, a c, d, a c, d, a switch downloaded from: http:///
in = 2.4v, all others = 0.8v dg411/dg412/dg413 improved, quad, spst analog switches _______________________________________________________________________________________ 3 electrical characteristics?ual supplies (continued)(v+ = 15v, v- = -15v, v l = 5v, v gnd = 0v, v inh = 2.4v, v inl = 0.8v, t a = t min to t max , unless otherwise noted.) ns ns -5 5 t a = t min to t max -5 5 t a = t min to t max t a = +25? -5 5 t a = t min to t max -5 5 t a = t min to t max t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = +25? in = 0.8v, all others = 2.4v t a = +25? conditions t a = +25? -1 -0.0001 1 all channels on or off,v+ = 16.5v, v- = -16.5v, v in = 0v or 5v all channels on or off,v+ = 16.5v, v- = -16.5v, v in = 0v or 5v all channels on or off,v+ = 16.5v, v- = -16.5v, v in = 0v or 5v pf 35 f = 1mhz, figure 8 c d(on) + c s(on) drain on-capacitance pf 9 f = 1mhz, figure 7 c d(off) drain off-capacitance pf 9 f = 1mhz, figure 7 c s(off) source off-capacitance db 85 r l = 50 , c l = 5pf, f = 1mhz, figure 6 crosstalk (note 6) db 68 r l = 50 , c l = 5pf, f = 1mhz, figure 5 oirr off-isolation (note 5) pc 51 0 c l = 1.0nf, v gen = 0v, r gen = 0 , figure 4 q charge injection (note 3) ns 25 dg413 only, r l = 300 , c l = 35pf, figure 3 t d break-before-make time delay v d = ?0v, figure 2 v d = ?0v, figure 2 160 t off turn-off time 100 145 220 t on turn-on time ? -0.500 0.005 0.500 i inh 110 175 input current with input voltagehigh -1 -0.0001 1 ? i gnd ground current ? -1 0.0001 1 i l logic supply current ? -1 0.0001 1 i+ positive supply current ? ? -0.500 0.005 0.500 i inl input current with input voltagelow all channels on or off,v+ = 16.5v, v- = -16.5v, v in = 0v or 5v v i- negative supply current ?.5 ?0.0 power-supply range units min typ max (note 2) symbol parameter input supply dynamic downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches 4 _______________________________________________________________________________________ electrical characteristics?ingle supply(v+ = 12v, v- = 0v, v l = 5v, v gnd = 0v, v inh = 2.4v, v inl = 0.8v, t a = t min to t max , unless otherwise noted.) note 2: the algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. note 3: guaranteed by design. note 4: ? r on = ? r on max - ? r on min. on-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. flatness is defined as the difference between the maximum and minimum value of on-resistanceas measured at the extremes of the specified analog signal range. note 5: off-isolation = 20log(v d/ v s ) , v d = output, v s = input to off switch. see figure 5. note 6: between any two switches. see figure 6. note 7: leakage parameters i s(off) , i d(off) , and i d(on) are 100% tested at the maximum-rated hot temperature and guaranteed by correlation at +25?. -5 5 t a = +25? t a = t max -5 5 t a = t max -5 5 t a = t max 315 t a = t min to t max -5 5 t a = t max t a = +25? t a = +25? t a = t min to t max t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? t a = t min to t max conditions pc 51 0 c l = 1.0nf, v gen = 0v, r gen = 0v, figure 4 q charge injection(note 3) ns 25 dg413 only,r l = 300 , c l = 35pf, figure 3 t d break-before-make time delay v s = 8v, figure 2 v s = 8v, figure 2 all channels on or off,v l = 5.25v, v in = 0v or 5v all channels on or off,v+ = 13.2v, v in = 0v or 5v all channels on or off,v l = 5.25v, v in = 0v or 5v all channels on or off,v+ = 13.2v, v in = 0v or 5v v+ = 10.8v,v d = 3.8v, i s = -10ma ns 140 t off turn-off time 40 80 95 125 t on ns 175 250 v 01 2 v analog turn-on time ? -1 -0.0001 1 i gnd analog signal range ground current ? -1 0.0001 1 i- negative supply current ? -1 0.0001 1 i l ? -1 0.0001 1 i+ positive supply current logic supply current 100 r ds(on) drain-source on-resistance units min typ max (note 2) symbol parameter switch supply dynamic (note 3) downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches _______________________________________________________________________________________ 5 60 -20 -10 10 on-resistance vs. v d and power-supply voltage 0 40 dg411-01 v d (v) r ds(on) ( ) 02 0 20 5030 10 70 a b c d a: v+ = 5v, v- = -5v b: v+ = 10v, v- = -10v c: v+ = 15v, v- = -15v d: v+ = 20v, v- = -20v 0 -20 -10 10 on-resistance vs. v d and temperature 50 dg411-02 v d (v) r ds(on) ( ) 02 0 30 10 4020 60 v+ = 15vv- = -15v t a = +125 c t a = +85 c t a = +25 c t a = -55 c 20 05 1 5 on-resistance vs. v d and temperature (single supply) 120 dg411-03 v d (v) r ds(on) ( ) 10 20 80 40 100 60 140 v- = 0v v+ = 5v v+ = 10v v+ = 15v v+ = 20v 160 20 05 1 5 on-resistance vs. v d (single supply) 70 dg411-04 v d (v) r ds(on) ( ) 10 20 50 30 6040 80 v+ = 12vv- = 0v t a = +125 c t a = +85 c t a = +25 c 0.0001 -55 off-leakage currents vs. temperature 10 dg411-05 temperature ( c) off-leakage (na) +25 +125 0.1 0.001 1 0.01 100 v+ = 16.5vv- = -16.5v v d = 15v v s = 15v 0.0001 -55 on-leakage currents vs. temperature 10 dg411-06 temperature ( c) on-leakage (na) +25 +125 0.1 0.001 1 0.01 100 v+ = 16.5vv- = -16.5v v d = 15v v s = 15v __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) -60 -20 charge injection vs. analog voltage 40 dg411-07 v d (v) q (pc) 02 0 0 -40 20 -20 60 -15 -10 -5 5 10 15 v+ = 15vv- = -15v v l = 5v cl = 1nf 0.0001 -55 supply current vs. temperature 10 dg411-08 temperature ( c) i+, i-, i l ( a) +25 +125 0.1 0.001 1 0.01 100 a: i+ at v+ = 16.5vb: i- at v- = -16.5v c: i l at v l = 5v a bc downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches 6 _______________________________________________________________________________________ __________applications information operation with supply voltages other than 15v using supply voltages other than 15v will reduce theanalog signal range. the dg411/dg412/dg413 switch- es operate with ?.5v to ?0v bipolar supplies or with a +10v to +30v single supply; connect v- to 0v when operating with a single supply. also, all device types can operate with unbalanced supplies such as +24v and -5v. v l must be connected to +5v to be ttl com- patible, or to v+ for cmos-logic level inputs. the typical operating characteristics graphs show typical on-resistance with ?5v, ?0v, and ?v supplies.(switching times increase by a factor of two or more for operation at ?v.) overvoltage protection proper power-supply sequencing is recommended forall cmos devices. do not exceed the absolute maxi- mum ratings because stresses beyond the listed rat- ings may cause permanent damage to the devices. always sequence v+ on first, followed by v l , v-, and logic inputs. if power-supply sequencing is not possi-ble, add two small, external signal diodes in series with supply pins for overvoltage protection (figure 1). adding diodes reduces the analog signal range to 1vbelow v+ and 1v below v-, without affecting low switch resistance and low leakage characteristics. device operation is unchanged, and the difference between v+ and v- should not exceed +44v. v+ s v- d v g v+ v- figure 1. overvoltage protection using external blocking diodes pin description pin dip/so/tssop qfn name function 1, 16, 9, 8 15, 14, 7, 6 in1?n4 input 2, 15, 10, 7 16, 13, 8, 5 d1?4 analog switch drain terminal 3, 14, 11, 6 1, 12, 9, 4 s1?4 analog switch source terminal 4 2 v- negative-supply voltage input 5 3 gnd ground 12 10 v l logic supply voltage 13 11 v+ positive-supply voltage input?onnected to substrate ep exposed paddle (qfn only). connect ep to v+. downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches _______________________________________________________________________________________ 7 t r < 20ns t f < 20ns 50% 0v logic input v- -15v r l 300 d1 gnd c l includes fixture and stray capacitance. v out = v s ( r l ) r l + r ds(on) switch input in1 +3v t off 0v switch output 0.9 x v out 0.9 x v out t on v out switch output logic input logic input waveforms inverted for switchesthat have the opposite logic sense. v l v+ c l 35pf +5v +15v v out s1 0v repeat test for in and s, for loadconditions, see electrical characteristics. dg411dg412 dg413 50% 0.9 x v out1 +3v 0v0v logicinput switch output 2 (v o2 ) 0v 0.9 x v out2 t d t d logic input v- -15v r l2 gnd c l includes fixture and stray capacitance. s2 in v l s1 v out2 v+ +5v +15v c l2 v s1 = +10v v s2 = +10v r l1 v out1 c l1 r l = 300 c l = 35pf d1 d2 switchoutput 1 (v o1 ) dg413 figure 2. switching-time figure 3. dg413 break-before-make ______________________________________________timing diagrams/test circuits v gen gnd d c l v out -15v v- v+ v out in off on off v out q = ( v out )(c l ) s +5v in depends on switch configuration;input polarity determined by sense of switch. off on off in v in = +3v +15v r gen in v l dg411dg412 dg413 figure 4. charge-injection downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches 8 _______________________________________________________________________________________ figure 6. crosstalk in 0v or 2.4v signalgenerator +15v c v l analyzer d r l gnd s c -15v v- +5v v+ dg411dg412 dg413 signalgenerator 0dbm +15v c analyzer d r l gnd s c v- -15v 0v or 2.4v in1 d 50 v l s +5v in2 0v or 2.4v v+ dg411dg412 dg413 figure 5. off-isolation _________________________________timing diagrams/test circuits (continued) capacitance meter d s gnd c v- -15v in 0v or 2.4v c +15v v l +5v f = 1mhz v+ dg411dg412 dg413 capacitance meter d s gnd c v- -15v in 0v or 2.4v c +15v v l +5v f = 1mhz v+ dg411dg412 dg413 figure 7. channel off-capacitance figure 8. channel on-capacitance downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches _______________________________________________________________________________________ 9 ordering information (continued) chip topography s3 s4 d3 0.097" (2.46mm) 0.080" (2.03mm) v- gnd d4 in4 in3 v l v+ s2 d1 in1 in2 s1 d2 ? contact factory for dice specifications. * ep = exposed pad. ** contact factory for availability and processing to mil-std-883b. *** contact factory for availability. part temp range pin-package dg411ege -40? to +85? 16 qfn-ep* dg411dj -40? to +85? 16 plastic dip dg411dy -40? to +85? 16 narrow so dg411dk -40? to +85? 16 cerdip dg411ak -55? to +125? 16 cerdip** dg411my/pr -55? to +125? 16 so*** dg411my/pr-t -55? to +125? 16 so*** dg412 cj 0? to +70? 16 plastic dip dg412cue 0? to +70? 16 tssop dg412eue -40? to +85? 16 tssop dg412cy 0? to +70? 16 narrow so dg412c/d 0? to +70? dice? dg412dj -40? to +85? 16 plastic dip dg412ege -40? to +85? 16 qfn-ep* dg412dy -40? to +85? 16 narrow so dg412dk -40? to +85? 16 cerdip dg412ak -55? to +125? 16 cerdip** dg412my/pr -55? to +125? 16 so*** dg412my/pr-t -55? to +125? 16 so*** dg413 cj 0? to +70? 16 plastic dip dg413cue 0? to +70? 16 tssop dg413eue -40? to +85? 16 tssop dg413cy 0? to +70? 16 narrow so dg413c/d 0? to +70? dice? dg413ege -40? to +85? 16 qfn-ep* dg413dj -40? to +85? 16 plastic dip dg413dy -40? to +85? 16 narrow so dg413dk -40? to +85? 16 cerdip dg413ak -55? to +125? 16 cerdip** downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches 10 ______________________________________________________________________________________ 16 d1 15 in1 14 in2 13 d2 5 d4 6 in4 7 in3 8 d3 dg411 2v- 1 s1 3 gnd 4 s4 11 v+ 12 s2 10 v l 9 s3 top view 16 d1 15 in1 14 in2 13 d2 5 d4 6 in4 7 in3 8 d3 dg412 2v- 1 s1 3 gnd 4 s4 11 v+ 12 s2 10 v l 9 s3 16 d1 15 in1 14 in2 13 d2 5 d4 6 in4 7 in3 8 d3 dg413 2v- 1 s1 3 gnd 4 s4 11 v+ 12 s2 10 v l 9 s3 qfn qfn qfn *ep = connect ep to v+. pin configurations/functional diagrams (continued) downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches ______________________________________________________________________________________ 11 package type package code document no. 16 qfn-ep g1655-3 21-0091 16 plastic dip p16-1 21-0043 16 tssop u16-2 21-0066 16 cerdip j16-3 21-0045 16 narrow so s16-1 21-0041 16 so s16-1 21-0041 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . downloaded from: http:///
dg411/dg412/dg413 improved, quad, spst analog switches maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 6 9/07 addition of exposed pad information 1, 6, 9, 14, 15 7 9/08 addition of rugged plastic information 1, 9 downloaded from: http:///

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